Galactic Matyhematics.

Fine, then I didn't do division either and still got the answer in a third of the time.

You've said lots of things but since they fail to stand up to inspection, I don't know why you would expect us to believe something on your word. What "field of it" do you want us to believe is so restrictive that these rules would have application?

1) VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics by Himanshu Thapliyal


This paper proposes the hardware implementation of RSA encryption/decryption algorithm using the algorithms of Ancient Indian Vedic Mathematics that have been modified to improve performance. The recently proposed hierarchical overlay multiplier architecture is used in the RSA circuitry for multiplication operation. The most significant aspect of the paper is the development of a division architecture based on Straight Division algorithm of Ancient Indian Vedic Mathematics and embedding it in RSA encryption/decryption circuitry for improved efficiency.The coding is done in Verilog HDL and the FPGA synthesis is done using Xilinx Spartan library. The results show that RSA circuitry implemented using Vedic division and multiplication is efficient in terms of area/speed compared to its implementation using conventional multiplication and division architectures.

2) Time-Area- Power Efficient Multiplier and Square Architecture Based On Ancient Indian Vedic Mathematics by Himanshu Thapliyal and Hamid R.Arabnia

In this paper new multiplier and square architecture is proposed based on algorithm ancient Indian Vedic Mathematics, for low power and high speed applications. It is base on generating all partial products and their sums in one step. The design implementation is described in both at gate level and high level RTL code (behavioural level) using Verilog Hardware Description Language. The design code is tested using Veriwell Simulator.

The code is synthesized in Synopys FPGA Express using: Xilinx,Family: Spartan Svq300, Speed Grade: -6. The present paper relates to the field of math coprocessors in computers and more specifically to improvement in speed and power over multiplication and square algorithm implemented in coprocessors. In FPGA implementation it has been found that the proposed Vedic multiplier and square are faster than array multiplier and Booth multiplier.

3) A High Speed and Efficient Method of Elliptic Curve Encryption Using Ancient Indian Vedic Mathematics by Himanshu Thapliyal and M.B.Srinivas

Abstract—This paper presents for point doubling using square algorithms of Ancient Indian Vedic Mathematics. In order to calefficient hardware circuitry culate the square of a number, “Duplex” D property of binary numbers is proposed. A technique for computation of fourth power of a number is also being proposed. A considerable improvement in the point additions and doubling has been observed when implemented using proposed techniques for exponentiation.

3)The Implementation of Vedic Algorithms in Digital Signal Processing by Purushottam D. Chidgupkar and Mangesh T. Karad


Digital signal processing (DSP) is the technology that is omnipresent in almost every Engineering discipline. It is also the fastest growing technology this century and, therefore, it poses tremendous challenges to the engineering community. Faster additions and multiplications are of extreme importance in DSP for convolution, discrete Fourier transforms digital filters, etc. The core computing process is always a multiplication routine; therefore, DSP engineers are constantly looking for new algorithms and hardware to implement them. Vedic mathematics is the name given mto the ancient system of mathematics, which was rediscovered, from the Vedas between 1911 and 1918 by Sri Bharati Krishna Tirthaji. The whole of Vedic mathematics is based on 16 sutras (word formulae) and manifests a unified structure of mathematics. As such, the methods are complementary, direct and easy. The authors highlight the use of multiplication process based on Vedic algorithms and its implementations on 8085 and 8086 microprocessors, resulting in appreciable savings in processing time. The exploration of Vedic algorithms in the DSP domain may prove to be extremely advantageous. Engineering institutions now seek to incorporate research-based studies in Vedic mathematics for its applications in various engineering processes. Further research prospects may include the design and development of a Vedic DSP chip using VLSI technology.

Discrete Fourier Transform (DFT) by using Vedic Mathematics by Shripad Kulkarni.


Though there are many algorithms for the same task only VAN-NEUMAN architectural implementation of classical method is found to be used in present day digital computers.

The Vedic mathematical methods suggested by Shankaracharya Sri. Bharti Krishna Tirthaji through his book offer efficient alternatives. The present seminar analyses and compares the implementation of DFT algorithm by existing and by Vedic mathematical technique . It is suggested that architectural level changes in the entire computation system to accommodate the Vedic mathematical method shall increase the overall efficiency of DFT procedure.

Kunal Singh and Vinesh Raicha are pursuing Masters of Science in Computer Science and their partner Rohit Jog who is also an MSc in Computer Science is currently working with Symantec.They show some Vedic Math Algorithm Applications in their Paper and show other useful application of Vedic Math in the field of IT with their diagrams

Application of Vedic Mathematics In Computer Architecture
Chilton Fernandes1, Samarth Borkar2

1(Microelectronics, Goa College of Engineering, Goa University, India)
2(Assistant professor, Goa College of Engineering, Goa University India)

ABSTRACT: Vedic mathematics or ancient mathematics is a unique technique of calculations based on 16 sutras. It provides an innovative way of computation of almost all the mathematical operations. In this era of digitization, engineers are working on increase speed of the digital circuits while reducing the size and power consumed. Arithmetic operations are the basic units of all the digital circuitry and hence optimizing these unit increases efficiency of the entire digital design. Unlike conventional mathematics, Vedic math provides different techniques to compute basic arithmetic operations. Vedic math reduces the computational steps required to achieve the result. Designers have implemented many computer architectures based on Vedic math. In this paper we review these architectures as well as several extended work in the area. In addition, we also review several state-of-art applications that take full advantage of such simple ancient Vedic Mathematical technique.
Keywords - Nikhilam sutra, RSA algorithm, Urdhva-tiryakbyham, Vedic mathematics, Vedic multiplier

Quote:

IMPLEMENTATION OF FIXED AND FLOATING POINT DIVISION USING DHVAJANKA SUTRA

This paper proposes the implementation of RSA encryption/ decryption algorithm using the algorithms of Ancient Indian Vedic mathematics that has been modified to improve the performance. The recently proposed divider architecture is used in RSA circuitry for division operation. The most significant aspect of this paper is the development of division architecture based on straight division algorithm of ancient Vedic mathematics and embedding it in RSA encryption/decryption circuitry for improved efficiency. The modification that has been attained is done in the addition circuitry of the division architecture. The coding is done in Verilog HDL and FPGA synthesis is done using Xilinx Spartan library. The results show that RSA circuitry implemented using Vedic division is efficient in terms of area and speed, compared to its implementation using conventional division architecture. Index terms: Vedic math’s, Different Division Architecture, Dhvajanka sutra, RSA algorithm.

Key exchange protocol using vedic mathematics

Implementation of Diffie Hellmann Key Exchange protocol using Vedic Mathematics

Diffie-Hellman key exchange (D-H) is a commonly existent cryptographic protocol that allows two parties having no prior knowledge about each other to jointly share a secret key over an insecure communications channel. This key is used to encipher the subsequent communications using a symmetric key cipher such as DES etc., Vedic mathematics is the name given to the ancient system of mathematics, which was rediscovered, from the Vedas between 1911 and 1918 by Sri Bharathi Krishna Tirthaji. The whole of Vedic mathematics is based on 16 sutras (word formulae) and manifests a unified structure of mathematics. In this paper, implementation of the prime number multiplication and power calculation are demonstrated using Vedic mathematics for generating the keys and exchange it via the communication channel.

A Novel Approach to Design High Speed Arithmetic Logic Unit Based On Ancient Vedic Multiplication Technique

Abstract: This paper is devoted for designing high speed arithmetic logic unit. All of us know that ALU is a module which can perform arithmetic and logic operations. The reason behind choosing this topic as a research work is that, ALU is the key element of digital processors like as microprocessors, microcontrollers, central processing unit etc. Every digital domain based technology depends upon the operations performed by ALU either partially or whole. That’s why it highly required designing high speed ALU, which can enhance the efficiency of those modules which lies upon the operations performed by ALU. The speed of ALU greatly depends upon the speed of multiplier. There are so many multiplication algorithms exist now-a-days at algorithmic and structural level. Our work proved that Vedic multiplication technique is the best algorithm in terms of speed. Further we have seen that the conventional Vedic multiplication hard wares have some limitations. So to overcome those limitations a novel approach has been proposed to design the Vedic multiplier with the use of unique addition tree structure, which is used to add partially generated products. For designing the two bit Vedic multiplier conventional hardware of Vedic multiplier has been used. For designing the four and eight bit level Vedic multiplier divide and conquer approach has been used. After designing the proposed Vedic multiplier, it has been integrated into an eight bit module of arithmetic logic unit along with the conventional adder, subtractor, and basic logic gates. The proposed ALU is able to perform three different arithmetic and eight different logical operations at high speed. All of these operational sub-modules (adder, subtractor, multiplier and logical gates) have been designed as the combinatorial circuit. And for the synchronization of these operational sub-modules, the multiplexers which have been used to integrate these sub-modules in a single unit have been triggered by positive edge clock To design proposed arithmetic logic unit verilog hardware description language (HDL) has been used. For designing operational sub-modules data flow modeling and for integration purpose behavioral modeling style has been used. For this design the target FPGA which we have takes belongs to Virtex-2P (family), XC2VP2 (device), FG256 (package) with speed grade of -7. For synthesis purpose Xilinx synthesis tool (XST) of Xilinx ISE-9.2i has been used The behavioral simulation purpose ISE simulator has been used.

ECC ENCRYPTION SYSTEM USING ENCODED MULTIPLIER AND VEDIC MATHEMATICS


ABSTRACT: This paper presents an efficient design and implementation of ECC Encryption System using Encoded
Multiplier. ]ECC algorithm is implemented based on ancient Indian Vedic Mathematics. The speed of the system mainly depends on multipliers and adders. To improve the speed of the system, the multiplier architecture is modified using a new encoded algorithm. Using this algorithm number of partial products in the multiplier architecture is reduced to half
and thus it speeds up the operation. Effectively no multipliers are required and number of adders required is reduced
drastically. The most significant aspect of this paper is the development of encoded architecture and embedding it in
Point Multiplication circuitry of ECC algorithm. The coding is done in Verilog HDL and FPGA implementation using
Xilinx Spartan 6 library.

An advancement in the N×N Multiplier Architecture Realization via the Ancient Indian Vedic Mathematics

Abstract
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Multiplication is an crucial unfussy, basic function in arithmetic procedures and Vedic mathematics is a endowment prearranged for the paramount of human race, due to the capability it bestows for quicker intellectual computation. This paper presents the effectiveness of Urdhva Triyagbhyam Vedic technique for multiplication which cuffs a distinction in the authentic actual development of multiplication itself. It facilitates parallel generation of partial products and eradicates surplus, preventable multiplication steps. The anticipated N×N Vedic multiplier is coded in VHDL (Very High Speed Integrated Circuits Hardware Description Language), synthesized and simulated using Xilinx ISE Design Suite 13.1. The projected architecture is a N×N Vedic multiplier whilst the VHDL coding is done for 128×128 bit multiplication process. The result shows the efficiency in terms of area employment and rapidity.

These papers are hysterical! "VM" was created in the '60s but these keep referring to "Ancient Indian Vedic Mathematics." Are you pushing this as part of the Hindu Nationalist movement? I love this line. This has to be the best start to a "math" paper ever: "Multiplication is an crucial unfussy, basic function in arithmetic procedures and Vedic mathematics is a endowment prearranged for the paramount of human race". Please tell me you don't really believe anyone would actually waste time using this stuff.

As to your assertion that you are not doing division but subtraction over and over again, that is one technique used to teach young children, but once you memorize your multiplication tables, no one does division that way since it is slow and tedious. I'm not sure what you think division is, but what you are doing is in no way different than division except that it is more time consuming. My guess is that you really do this stuff in your head using division. I can't picture you really sitting there subtracting 17 from 100 over and over again to get a remainder.

Have you ever considered that it is not the rest of the world that is deluded by their study of mathematics? That when it takes you forever to compute 1/17 or 1/7 when everyone else around the world can do it faster and more simply using techniques developed independently from a variety of cultures that maybe you're the one that has become indoctrinated and biased.

1/(x+4) + 1/(x+3)=1/(x+2) + 1/(2x+11) using VM.

Now, for something different, calculate

1/(x+4) + 1/(x+3)=1/(x+2) + 1/(x+5) the conventional way!

I deliverd proof Vedic Math is used in IT.

No you didn't. You just posted religious tracts that claimed that Vedic Math is used in IT.

I work in IT and I understand the RSA algorithm. This religious marketing campaign is rather pathetic.

These are probably the same people who would deny 'free energy' or 'over unity' devices.
They are so blinded by their indoctrination that if you show them these things they will look foor the hidden battery! (of which there is none of course)

I deliverd proof Vedic Math is used in IT.

Oh and yes, Vedic Mathematics IS very ancient! Any idea when the Veda's were written???

1 / (x+3) + 1/ (x+4)=1/(x+5) + 1/(x+2)