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Mon 28 Nov, 2005 08:59 am
I know it involves synchronising the sampling by "off to on" transistions as opposed to "on to off" transitions in normal clocking, but I am unsure why it is implemented and under what situations it is suggested to use it.
I can't find a good article on its uses and how it operates, I was hoping someone could help me with this
Triggering on the falling edge of the clock pulse is often used when you have noise on the clock lines.
Noise or spikes are usually manifest as very sharp increases in voltage over a short timescale.
The steep risetime of the noise spike can be mistaken by the following circuitry as an actual clock pulse.
This leads to timing inaccuracies and false or ghost triggering.
It's easy to implement a filter to eliminate the spikes but it still leaves you with other longer-timescale anomalies that can also cause erronious triggering.
If you trigger on the negative-going edge you're a lot less likely to be affected by noise or other factors influencing triggering because there aren't many anomalous phenomena that stay high for a while and then fall at exactly the wrong moment.
Anomalies usually come and go very quickly.
hmm, so is it always best to use an inverted clock? are there times when it will be detrimental to do so? for example i found this on a site:
"Typical delays indicate that the inverted clock may be appropriate above 1.3 megabits per
second (Mbps), depending upon the DTE clock-to-data skews and setup required, and allowing some margin for temperature, cable, and other variables. Some DCE devices will not accept SCTE, so Serial Clock Transmit (SCT) must be used. Inverting the clock may be the only way to compensate for the cable length and circuit delays in the DTE and DCE."
This suggests that inverted clocks are appropriate for higher speeds yet are not recommended except for certain situations.
Nope.
Nowt to do with the speed.
It's to overcome the extra noise, random phase errors, ground lifts and other rubbish on the cable due to it's extra length.
Basically they're wanting/needing to use a longer cable than the design specs suggest. This introduces all sorts of other issues, noise and signal loss due to the extra attenuation over the length of the cable being the primary ones.
So they suggest using a -ve edge trigger to ensure that the noise doesn't cause problems.
It's a technique you can use to avoid spending more money. It's just a way of squeezing more bandwidth and performance out of the cable you have to hand.
There are other ways in which you could overcome the losses and extra noise of a longer cable but they're pretty much all expensive or involve extra circuitry which is also expensive.
Low loss cables, transparent buffer amps with a huge bandwidth, opto-couplers etc... All expensive stuff.
Simply inverting the clock with a high slew-rate not gate would be the way to go.
A Schmitt triggered inverting buffer IC would be my choice but naturally I don't know exactly what the application is.
Thanks for the comprehensive answer Helio

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