PLL questions

I have the following connection:

Sync dte - dce (rcv) - dce (int) - dce (ext) - dce (rcv) - sync dte

i'm aware the clocking is far from ideal, but I have been given a
scenario and there are certain aspects of it that i'm not quite sure
about and i would appreciate expert opinions

1) Which pin in this connection is the most sensitive to PLL jittering
throughout the clocking system of the connection?

2) if there are clock slips occuring at that point how can the problem
be resolved with external hardware?

3) how can the clockslip problem be fixed without external hardware if
modem B doesn't have to be set to Internal, and you can play around
with the other modem's clocking as well?

4) if you could change modem B, what pin would you add to its rs232
interface (one which isn't standard) to support the original
situation's clocking problems?

As far as i know PLL jittering would only affect the transmit clock
since PLLs lock receive clocks in order to use them as transmit clocks,
but then again i'm new to the field

I'd really appreciate any help you can provide