The initial gates for the realization of the basic AND- and OR-gate in CMOS-technology are actually the NAND- and NOR-gate, to which then an inverter is added (the reasons for this will be discussed below). The essence of the NAND- and NOR-gate is the combination of the parallel plus- and the series minus-connection of transistors.
Let's see the electronic realizations of the NAND- and the NOR-gate.
At the NAND-gate (left) we see that in the upper part, which gravitates to the (+)battery pole (Vdd), there is a parallel connection of two PNP-MOSFETs, and in the lower part a series connection of two NPN-MOSFETs. The parallel plus-connection gives dominance to the rail which it gravitates to, that is, an opportunity to expand is given to it; thus in the results we get three pluses and one minus. This means when either in A or in B, or in both simultaneously arrives (–)signal, then at least one upper MOSFET becomes conductive, so that the plus from above will come down to the output. With the series connection the other sign (/rail) is reduced. For the minus to go up to the middle, A and B must receive (+)signal, so that both lower NPN-MOSFETs become conductive (and none of the upper ones), thus the minus from below climbs to the output.
In the case of the NOR-gate the parallel and the series connection are set vice versa, so that here dominates the minus.
Note that if we either in the NAND- or in the NOR-gate join the inputs A and B together, then the gates turn into inverters. So, in a sense, both NAND- and NOR-gate can be treated as expanded inverters with one transistor up and down, on one side in parallel, on the other side in series connection.
When at the output of each gate one more stage with an inverter is added, then we get the basic AND- and OR-gate. They have to be realized so, because to the battery plus-pole must be attached P-region and to the minus-pole N-region. This means that the upper transistors must be PNP, so that when at their inputs arrives minus, at the output appears plus, that is, we will always get reversed gates, and NAND and NOR are just such: from at least one ‘zero’ at the input, we get ‘one’ at the output (three ones total=NAND), from at least one ‘one’ at the input, we get ‘zero’ at the output (three zeros total=NOR).
To show one of the possible solutions for the realization of the XOR-gate, we will first introduce another significant ‘cell’ of CMOS-integrated circuits. It is called transmission gate (TG). On the left side of the figure below is shown one such. New in this gate is that one of the two signals, in our example it is B, does not arrive at the transistor’s middle part (so-called Gate), but at the one of the outer parts (so-called Source). Whatever signal arrives at B, it will not pass through to the output if there is an ‘one’ at A, and it will do it only if there is a ‘zero’ at A (this case is shown in the figure with (0) at A and at the PNP-MOSFET and with (1) after the inverter). When there is a ‘zero’ at A, then the gates of both transistors have corresponding signals, thus the TG is conductive. If at that moment there is (1) at B, it will pass through the lower PNP-transistor; with (0) at B, through the upper NPN. It would be wrong for this logic gate to present a truth table as in the middle figure below, because when there is (1) at A, then the output does not have any signal, and the last two zeros in the column ‘OUT’ cannot represent "no signal", but they are a minus signal. Therefore, in the last two places of that column should be an X in each, if we agree X to mean "no signal". [footnote 5]
When in some logic circuits the possibility of not having any signal at the output (so-called ‘high impedance state’) is purposefully implemented, which is not rare, then it is called ‘three-state logic’. [end of footnote]
In case the inverter is relocated in the branch with the PNP-MOSFET, the signal from B will pass through the TG only if A has (1), that is to say, the opposite from the previous case will happen.
To the right of the figure is shown an XOR-gate realized with transmission gates. A' is connected to A via an inverter, and the same is true for B' to B. These inverters are not drawn for greater simplicity. We have still drawn one with dashed lines. When A=0, then only the upper TG is conductive, so whatever at that moment is present at B, it will be transmitted to OUT. When A=1, then only the lower TG is conductive, and since here enters B', at the output will be ‘copied’ the reversed values of B (see the truth table for the XOR-gate).
In order to realize an XNOR-gate, we don’t have to add an inverter after the previously described gate; rather, we have only to change the places either of A and A' or of B and B'.
With little thought we can conclude that in this balanced gate we have something very similar to the fans from the beginning of this answer.
For some tasks executed by the computer one gets the impression that it performs them simultaneously, but sometimes it is an illusion, because it often jumps from one unfinished operation to another, then to a third, to a fourth etc., and then goes back to the first one and so on in circles until every task is done. However, the electric current does this with tremendous speed, so we have the impression that it all happens simultaneously. In the logic circuits mentioned above the signal will pass through to the last stage without waiting anywhere. But it often has to wait somewhere until it comes its turn to resume. The logic circuit enabling this is called a flip-flop.
The flip-flop has two inputs. The one is called ‘set’, the other ‘reset’, and two outputs, Q and Q' (figure below). The flip-flops are also called bistable devices. This means that they can have two stable, but inverse states at the output: the first state is Q=1, Q'=0, and the second Q=0, Q'=1. Q and Q' must always be different, which is symbolically expressed by the bar over one Q. These building cells are nothing other than holders (i.e. memory storage elements) for some time of one bit (BInary digiT), that is, of one ‘one’ or one ‘zero’. The convention is that the holder of this 1-bit information is the Q-output.
Operational is the (+)current (i.e. the ‘one’) because the positive logic is in force. When at the S-input arrives (1), then the R-input should have (0); then at Q must appear (1), and at Q' (0). This is called SET. When at R-input arrives (1), then the S-input should have (0); then at Q must appear (0) and at Q' (1). This is called RESET. The two inputs S-R must not, that is, should not have (1) at the same time. If there is a zero on both inputs (which is allowed), then it must not affect the previously established state.
The basic bistable elements are built using two NAND- or two NOR-gates.
Note some details on the figures above. The NAND-FF has bars, i.e. negations over S and R, and at the NOR-FF there is no such thing; but here R is up and S is down, which is not in accordance with the usual practice, S to be up and R down.
To see what is going on, we will draw the two circuits completely (figure below).
On both figures we see that the S-input operates two MOSFETs [one PNP (A1) and one NPN (B1)] in the upper gate, and also the input R, but in the lower gate. The other two transistors in the upper gate (A2 and B2) are operated by the output of the lower gate, and those in the lower gate are operated by the output of the upper gate.
When in the electric schemes two wires cross (+) and the crossover point is not thickened, it means that there is no contact between those wires.
Let's see what's happening with NAND-FF (the figure left). If at the input S arrives minus, then A1 becomes conductive and the plus from the plus-rail goes down to Q. This plus goes down to A2' and B2' too. On A2' it has no effect, but on B2' it does. When S=0, then R should be (1). This means that both series MOSFETs in the lower NAND-gate have a (+)signal at their inputs, thus both become conductive, so the minus from below climbs to Q'. This minus goes up to A2 and B2 too. It only affects A2, so the second MOSFET at the top is also conducting, which is not necessary.
Similarly we can derive the opposite situation: when S=1, R=0. Then both Q and Q' will be with inverse values compared to the previous case.
If both inputs S and R get (–), then both outputs become (+).
If both inputs S and R get (+), then it will have no effect on the previously established state because only one (+)transistor from both series connections becomes conductive, which is not enough.
Now let's look at the NOR-FF. If at the input R arrives (+), then B1' becomes conductive, thus the minus climbs in the Q'. It will climb to B2 and A2 too. Only A2 becomes conductive. When R gets (+), S should get (–). This means that A1 is also conductive. The two series A1 and A2 are conductive, so the plus goes down to Q. It will descend to B2' also, thus making it conductive, which is not necessary.
If both inputs S and R get (–), then it will have no effect on the previously established state.
If both inputs S and R get (+), then both outputs become (–).
In the tables below we see the summarized states in NAND- and NOR-FF.
The repetition of Q and Q' in the results means that the input signals have no effect on the previously established values of Q and Q'.
Since we work with positive logic, the ‘one’ has the active role. But two ‘ones’ at the input should not occur. Two ‘zeros’ at the input must not have an effect on the previously established state. When S=1, the agreement is Q to be 1, and when R=1 the agreement is Q' to be 1. (The information carrier is the Q-output.)
If we look at the tables we see that none of them meets the requirements just said. NAND-FF does not fulfill the requirement when S=1 then Q to be 1, also in relation to R, and neither the requirement that two zeros at the input should have no effect. NOR-FF does not meet only the first two of those about the NAND-FF. Therefore, the circuits must be adjusted so that they will meet the requirements. If we connect one inverter on each of the two inputs of the NAND-FF, and on each of the two outputs of the NOR-FF, then the requirements will be met. The contrast is also seen here: in the first we add inverters to the inputs, in the second to the outputs. But in the case of NOR-FF the problem can be solved more easily, whereby saving one stage in it by simply crossing the output leads. The lower lead will be directed up, and the upper lead down, which is identical to that, Q' to call Q, and Q to call Q'.
Now it becomes clear why in the symbol for the NAND-FF there are bars over the letters S and R (they represent the added inverters), and in the symbol for the NOR-FF the S-input is down, and the R is up (which is identical to that, Q and Q' to exchange their positions).
There is no need for two simultaneously generated signals to arrive at the flip-flop. It is possible that the S-R inputs through two equal resistors (say 1-10kΩ for each input) should be kept on negative potential, that is, through them to be connected to the battery minus-pole (two zeros at the inputs have no effect). Only a brief plus-signal to the S-input (which we can simulate by its brief direct connection to the battery plus-pole) will cause setting the flip-flop (direct connection means a maximal plus; at that moment the considerably weaker minus that comes through the resistor is canceled), in which condition it will remain even after the termination of this contact. Then only a brief contact of the R-input to the plus-pole will cause resetting the flip-flop.
For example, when we push the button on the elevator from outside, then we can imagine that for a short moment we connect S to the (+)pole of the source. At the output Q (which is via an LED-lamp connected to the (–)pole) appears a plus and the lamp in the button lights up. After releasing the button the lamp continues to shine, because now there is a minus on both inputs, which has no effect. When the elevator stops on our floor, then for a brief moment it connects the R-input with the (+)pole of the source. Now Q=0 and Q'=1, thus the lamp goes out. The output Q' is not connected to anything. If we put between it and the (–)pole a resistor and a lamp in another color, then, when the elevator is not called, a different color would shine, which would be more confusing than necessary.
In the case of the so-called Delay- or Data-flip flop (D-flip flop), the sole signal sent to it splits immediately at front of it in two lines, one of which goes directly to S and the other via an inverter to R. Thus, both inputs have always opposite signals.
Now we will extend the flip-flop with a third input, which we will connect to both S- and R-input via AND-gate each (figure below). This input is called "Enable" or "Control". Since the AND-gate gives (1) only when both or all of the inputs are (1), it follows that when ‘one’ waits either at S or at R, it will not pass through to the output if the Enable-input is (0). Therefore it is called "enable": only when (1) arrives at it, the flow is enabled.
In the first two of the three figures above, we see the same that we’ve discussed before: the left flip-flop from NAND-gates instead of two AND-gates at EN-input has two NAND-gates (two AND-gates and the two inverters in front of NAND-FF, which turns into two NAND-gates), and the flip-flop from NOR-gates (in the middle) has two AND-gates at EN-input, but here S instead of being up, it is down.
The input "EN" in the computer technology is very often a clock. A clock is an alternating change of the plus and the minus with a 50% duty cycle. The figure below shows a graph of a clock signal with a frequency of 1MHz, whose period is 1 microsecond (1μs). Since the duty cycle is 50%, it means that 0.5μs lasts the plus-, and just as much the minus-signal (30% duty cycle at 1MHz would mean that the plus-signal lasts 0.3μs and the minus-signal 0,7μs; the percentage always refers to the plus-signal). The third figure above shows the symbol for this flip-flop.
We can roughly simulate the clock by touching the input lead of the inverter to the plus and minus battery rail alternately at equal intervals.
The figure below shows a simple clock generator (also called an astable multivibrator) composed of two CMOS inverters, one capacitor and one resistor:
At the output of this circuit we get alternately 1-0 signals, i.e. a "square wave". In the figure on the left by means of the digits 1-0-1 is represented one of the two possible states in the circuit (the other is 0-1-0). When there is (1) at the output, the upper PNP-MOSFET of the second inverter is conducting. Then C1 is twisting (the electricity in a capacitor is actually twisting, which will be explained in other articles) along the line: (+)pole>the mentioned PNP>C1>R1>the lower NPN of the first inverter>(–)pole at the point B. During this twisting there is a (+)current from the point A to the first inverter, making its lower NPN conductive. When the capacitor is twisted close the maximum, then the (+)current to the first inverter becomes weak. At that moment comes into force the (–)current from the point B through the lower transistor, via R1, to the input of the first inverter (actually C1 and R1 act as a voltage divider). In this inverter the upper transistor now becomes conductive, whereby the capacitor starts to untwist, which further provides the (–)current from the point A to the first inverter. The capacitor is untwisting to zero and begins to twist in the opposite direction along the line: (+)pole>upper left PNP>R1>C1>lower right NPN>(–)pole at the point C, so that this time we have the opposite state (0-1-0). When the capacitor is twisted close to the maximum, then the same that we have just described is valid again (this time the (+)current to the first inverter will come through its upper transistor and the resistor). The output of the second inverter, as well as the output of the first, we can connect through one LED and one resistor at each to the battery (–)pole. They will light up alternately. The frequency depends on the values of the resistor R1 and the capacitor. With a 500-600nF capacitor and a 1MΩ resistor, we can get a frequency of approximately 1Hz. This clock signal from the output of this circuit can be used as an input for ‘Enable’ of the flip-flop.
If the output Q of the extended flip-flop is connected back to the R-gate, and the output Q' back to the S-input, then this flip-flop so to say closes in itself - only the clock-input remains free (the left figure below shows this flip-flop made up of NAND- and the middle figure of NOR-gates). This flip-flop will toggle at each positive part of the clock signal (this means: if at a given moment Q=1, Q'=0, then with the first next ‘one’ of CLK, Q becomes zero and Q' one). That's why it is called toggle-flip flop (T-flip flop).
However, in thus constructed T-flip flop there is one problem, the so-called "race around condition". If the clock is 1MHz, then the positive as well as the negative half-cycle is 0.5μs (=500ns). If the passing time of the signal through the flip-flop (propagation delay time), i.e. the time from the moment of arrival of the (+)signal at the input up to the moment of its appearance at the Q-output [simultaneously the (–)signal at Q'], is let’s say 50ns, then during only one positive half-cycle of the clock the values at Q and Q' will toggle 10 times. To avoid this, the positive half-cycles of the clock are immediately before entering the flip-flop transformed into brief positive impulses (as we will see, it can be done also with the negative half-cycles, but in negative impulses). This is called "edge triggering". The circuit that realizes this transformation is called "pulse detector circuit". It could also be said that this circuit drives the duty cycle to an extreme.
The figure below shows a simple circuit for positive impulses. The capacitor C is small and it will twist quickly along the line C>R>(–)pole when (1) appears at IN. During the twisting the plus-signal passes through the diode. Once the C is twisted, then through R comes a minus-voltage to D, but no current can pass through it. When the input after the (1) becomes (0), then the capacitor is untwisting through R, because both the left and the bottom point are minuses, i.e. it is a closed loop (the dashed line). During the untwisting there is (–)current towards the diode, but it has no effect on the output. Now C is untwisted and ready to twist again when a new (+)signal appears at the input.
We can easily turn this circuit into one for negative impulses. It is enough to turn the diode in the opposite direction and to move the resistor up, that is, to connect it to the battery plus-pole.
The figure below symbolically shows two T-flip flops, the first is sensitive to positive, the second to negative impulses. The difference is in the small circle at the clock input. The circuit for generating brief impulses is already an integral part of these flip-flops.
If at the input of any of these two flip-flops we connect a clock generator with a certain frequency, then at both outputs Q and Q' we get signals with twice lower frequency (frequency divider). These two signals are the same, only inverse. The twice lower frequency behind the flip flop is due to the fact that the triggering, which changes its state from plus to minus and vice versa, occurs only once during one full cycle of the clock. The left figure below shows the timing diagram of the clock and of the outputs of the flip-flop which is triggered on the rising edges of the clock (0→1), and on the figure on the right on the falling edges (1→0).
If we now use the output of this flip-flop as a clock signal for a next flip-flop, then at the output of the second we get twice lower frequency compared to the previous one, that is, four times lower frequency than the source clock. This has been used for construction of very important circuits in electronics, that is, of counters. What is a counter? Let's imagine a three-digit time counter that counts and shows seconds from 0 to 999. The first digit from the right changes once in a second (1Hz). The second changes ten times slower, i.e. once in ten seconds (0.1Hz), the third 100 times slower than the first (0.01Hz). So at each digit we have clocks with different frequencies, whose ratio is 1 : 1/10 : 1/100.
In our positional decimal numeral system [footnote 6] we have ten digits, or say ten states (0, 1, ... , 9). But if we have only two states available, then analogously to the previously described, the counting will look like the following figure:
The Hindu-Arabic decimal numeral system, which in the recent history is globally spread, is called a positional system because the value of a digit does not depend solely on itself, but also on the position it is located at (e.g. 2 means two, but 2 in 25 does not mean two, but twenty). The Roman numeral system is an example of a non-positional, that is, III means three, without the position of the signs playing a role. This system was in use in Europe until the 14th century. With its abandonment and the introduction of the Hindu-Arabic system, the calculation was significantly simplified, and at the same time the expressing of decimal point numbers (e.g. 2.75). [end of footnote]
If we imagine these 8 rows of circles as different states of three lamps that turn on and off, and each new row at the figure is a new state of the lamps at equal intervals (with the colored circle indicating a lamp turned on), then the frequency in the first column from the right is two times higher than that in the second, and this is also twice as high as that in the third column. This is called 3-bit counter. It can count from 000 to 111 (i.e. from 0 to 7) and is composed of three connected flip-flops:
The figures above show two counters that have the same function. The difference between them is that the first is made up of flop-flops triggered on the falling edges of the clock, while the second is made up of flip-flops triggered on the rising edges. As we see, the Q-outputs in the first counter are inputs for the next flip-flop, while in the second, the just said refers to the Q'-outputs. These counters are called up-counters.
Note the moment on the right figure when QA falls from 1 to 0 for the first time. Then B-FF is triggered. On the other hand we say that it reacts on rising edges. But at that moment Q'A changes from 0 to 1, and Q'A is the output which is connected to the clock input of the next flip-flop.
If each of the three Q-outputs through one LED-lamp and one resistor is connected to the battery minus-pole, then the lamps will turn on and off as described in the figure above with the circles, only we need to put QA QB QC in the order QC QB QA, that is, the figures with the flip-flops have to be drawn from right to left.
What will happen if we flip the connections in these two counters, i.e. in the left counter we connect the Q'-outputs to the clock inputs of the flip-flops, and in the right counter the Q-outputs? Then we get down counters.
Thus constructed counters will constantly count in a circle without pause. It is often necessary that they be put into operation or be stuck at a particular moment. Therefore, the T-flip flop needs to be extended with a new input. Such a flip-flop is shown in the left figure below.
When the new input, called T, is (1), then the flip-flop is active. When it is (0), the flip-flop is stuck, regardless of the fact that the clock continues ‘ticking’.
If we tear the T-connection of this flip-flop into two separate inputs, then we get the so-called universal or JK-flip flop, represented in the middle and the right figure (in fact J-K are S-R inputs, but in order to make a distinction from the simple S-R flip-flop, they are marked with two other successive letters of the alphabet). Returning the procedure back, that is, joining the J with the K-input, we get the T-input, and connecting the T-input to the plus battery-pole we get the T-flip flop. We said above that the inputs S-R (now J-K) must not be (1) at the same time. That’s just what is done here. But in every rule there is an exception.
These are the symbols for JK-flip flops, the first triggered on the positive, the second on the negative edges:
If we add an inverter from the J- to the K-input, then we get the very often used D-flip flop (Data- or Delay-flip flop):
Counters should often run in circle, however, not to their last possible number, but to a smaller one. For example, to display the decimal digits at least a 4-bit counter is needed. It should count from 0000 to 1001 (i.e. 0 to 9) and then return to 0000. These are called modulo ɳ-counters. The counter from 0000 to 1001 is called modulo-10 – MOD-10 counter.
To accomplish this, the JK- or the T-flip flops need another Reset-, also called Clear-input (CLR). In addition to it, they actually have another Set-, also called Preset-input (PRE), which we don’t need now. The figure below shows a JK-flip flop made up of NAND-gates with these two inputs. PRE and CLR (and not only they) may have or may have not a bar over them. What does this bar mean?
We said above that the digital electronics works mostly with positive logic, i.e. that the (+)current has the active role. But it is only basically. In fact the electronic circuits are constantly working with both positive and negative logic. Imagine that the MOD-10 counter is in the 0000 state and the digit zero should appear on the display. So, in the state of the outputs of only zeros, electronic circuits should be activated to turn on some lamps. Or another example: when we talked about the elevator we said that its motor will be actuated when the elevator is not overloaded. But the sensor will produce current, i.e. an (1) signal, just at overload, and zero at normal condition. Thus the elevator should start moving at a zero signal from the sensor, and since the circuits work with positive logic, this zero should be inverted into (1).
The JK-flip flop above, composed of NAND-gates, can be reset with a (0) at the CLR'-input. If it is composed of NOR-gates, then it can be reset with an (1) at the CLR-input, so this input will not have a bar over it. Before the CLR'-input of the NAND-FF we could add an inverter; then the bar over the CLR could be deleted.
So, the bar indicates that here we are working with negative logic, that is, the function ‘Clear’ will be executed when zero appears at the input. Such inputs are called ‘Active LOW’. When there is no bar, it is an "Active HIGH’ input.
Let's go back to the MOD-10 counter. It should count to 1001. At the moment when the next state occurs (1010), the counter should be zeroed. On the second and fourth position from right to left of this state there are ones. Such state cannot happen before. Therefore the outputs of the second and the fourth flip-flop are connected with AND-gate, whose output becomes (1) at the moment when 1010 occurs. This output is sent to the CLR-inputs of the flip-flops (in fact, not necessarily to all but only to the second and the fourth, but it is safer to all), making all Q-outputs suddenly become zero (figure below).
In this counter the state 1010, which is equal to our 10, still occurs for a very short moment. This can cause problems in high-frequency counters. In principle, the counter must be reset at the moment when the clock falls or rises (depending on the type of counter), so that ‘1010’ won’t happen at all. Before we describe the counter that solves this problem, let us mention something that should have been mentioned perhaps earlier.
When the first clock signal arrives at the input of the counter, then the appearance of the signal at the output of the first flip-flop will be 50 nanoseconds later if the "propagation delay time" for that particular type of flip-flop is that much. This output, i.e. the clocking of the first flip-flop is the input for the second, so that the output of the second will be 100ns belated relative to the source clock. The more bits the counter has, the longer the output of the last flip-flop is delayed (for a 10-bit counter, the output of the last FF will be delayed 10x50ns=500ns). That's why these counters are called asynchronous. In the case of fast counters, that is, for those who work with high frequencies of the source clock, the delay causes errors, thus they are constructed differently, i.e. as synchronous counters.
The figure below shows the counter mentioned above and its time diagram. This time the diagram shows the delays in the state changes of the flip-flops. The counter consists of JK-FFs and the "Clear" function is not used. Only those inputs and outputs that are in use are displayed.
All four flip-flops in this counter work somewhat different thanks to the possibilities offered by the JK-flip flops. The first A-FF operates as a T-flip flop with regular frequency (its J and K are attached to 1). The second B-FF also works as T-flip flop, but only while Q'D=1 (i.e. QD=0). The third C-FF works as T-flip flop, but since it takes the clock from its predecessor, its frequency is also not regular. The fourth D-FF works as T-flip flop when it is set, and as SR-flip flop when it is reset.
When the state 1000 (=8) occurs (i.e. the first switching of D), from then on the B and C should no longer switch. Therefore, the switching of D is used as a trigger for stopping of B (the output Q'D is connected to the J-input of B).
Since the falling of QA remains as the only possible trigger for resetting of D, it is necessary QA to be the clock-input for D. But to prevent its premature setting by this clock, QB and QC are via an AND-gate connected to the J-input of D. At the moment tx, when QA falls, QB and QC are (1), thus D will switch its state. Very shortly afterwards the QB&QC becomes zero, leaving D simply as an SR-FF at the next fall of QA to reset and further to remain indifferent to the switching of QA until the next timespan when QB&QC will be (1).
In synchronous counters, the clock signal enters all the flip-flops so that in a sense they can be called counters in parallel, and the asynchronous – counters in series connection. Synchronous counters must be built from JK-flip flops, for through them to be controlled which flip-flop at a given moment will be unlocked, and which locked. The image below shows a 4-bit synchronous counter.
The J-K inputs of the first A-FF are attached to the (+) so that with each fall of the clock (1→0) it will switch. The Q-output is connected to the J-K inputs of the second B-FF so that this one will switch if two conditions are met: one is the clock to fall and the other is QA=1. The third C-FF should switch when three conditions are met: the clock falls, QA=1, QB=1. Therefore, QA and QB are coupled via an AND-gate, whose output is input for the J-K of the C-FF. Analogously for the fourth D-FF. We can conclude all this just by looking at the table above. When the state 0011 occurs (i.e. QA=1, QB=1), then the conditions are fulfilled with the next clock pulse the third digit to switch its state (0→1). When the state 0111 occurs, then the conditions are fulfilled for the third digit to switch its state again (this time from 1→0), but also the fourth digit (from 0→1) and all the rest.
In the timing diagram we notice that all FF are switching simultaneously with equal delay behind the clock signal.
The counter is one of the essential circuits in digital electronics. Here is an example of its use in the multiplexer (MUX). The multiplexer is a circuit that converts the parallel into series connection. Let's say we have 4-bit information that comes in four parallel lines (parallel bus), and then it should continue in a single line (serial bus), something like a four-lane street which narrows into one lane. In the left figure below is shown a "4 to 1-bit" multiplexer. Each of the parallel lines (A,B,C,D) enters into an AND-gate. In these AND-gates enter also the outputs of a 2-bit counter (QA, Q'A, QB, Q'B). When the counter is in the initial state 00, then the A-lane signal will appear at the MUX-output, because the inverted values Q'A and Q'B (that is, 11) enter the uppermost AND-gate. At the next state of the counter 01, at the output will appear the signal of the B-lane, because into the second AND-gate enter QA and Q'B, which means 11. The OR-gate at the end "summarizes" the four lanes into one. In the figure on the right is shown a "1 to 4-bit" demultiplexer, which has the reverse function of the multiplexer.
For the “8 to 1-bit” multiplexer we need a 3-bit counter, for a “16 to 1-bit” a 4-bit counter.
At the outputs of the MOD-10 counter we can attach additional gates to display decimal digits (0...9) on a 7-segment display. This display is composed of 7 elongated LEDs (a1, b2, c3, d4, e5, f6, g7) arranged in the form of number 8. In order to display the digit zero, all the LEDs except g7 should be on, for the digit one only the LEDs b2 and c3. For each digit, there is one AND-gate with four inputs. When the counter is in the initial state 0000, on the display should be shown a zero. In that case the set 0000 should be inverted into 1111 (in order to save on inverters the Q'-outputs are used) and should be send to the first AND-gate, whereby only its output turns into (1). This (1) will be directed to the six LEDs: a1, b2, c3, d4, e5 and f6, but through one OR-gate in each line (for this gate we know that only one input needs to be 1 for the output to be 1). The output from the AND-gate must go through OR-gates to the LEDs and not directly for the following reason: to the same LEDs go also the outputs from the other AND-gates for the other digits. All these outputs have a state (0) when the first AND-gate has a state (1). If this output directly goes to the LEDs, then they would be bypassed by a short circuit between the output’s (1) (the +pole) and the zeros (the -pole) from the outputs of the other AND-gates.
Of course, after the OR-gates we add resistors in series with the LEDs, then it all goes to the minus-pole of the battery.
The reader should carefully consider the thick points on the schematic below for better understanding.
By adjusting the clock (capacitor/resistor in the clock generator), this display can also serve as a digital clock that counts 10 seconds. With another 3-bit MOD-6 counter and 7-segment display a clock can be made that counts 60 seconds.